Thursday October 20th
9:15 - 10:15
9:15 - 10:15
Enabling tinyML by exploiting heterogeneous multi-core AI processing
Prof. Marian Verhelst, KU Leuven
Abstract: tinyML strives for powerful machine inference in resource-scarce distributed devices. To allow intelligent applications at ultra-low energy and low latency, one needs 1.) compact compute and memory structures; 2.) which are used at very high utilization. This has resulted in a wide variety of accelerator designs proposed in the SotA. However, it becomes increasingly clear that every intelligent edge device will need to be equipped with a diverse set of many heterogeneous co-processors, which allow to run every workload at the most compatible (combination of) accelerators. Moreover, by using multiple cores in parallel, streaming data between the cores, the required amount of on-chip memory and IO bandwidth can be reduced, leading to area, energy and latency savings. This talk will introduce the benefits and challenges of such heterogeneous ML systems, supported through practical examples for efficient deep inference.
Marian Verhelst is a full professor at the MICAS laboratories of the EE Department of KU Leuven. Her research focuses on embedded machine learning, hardware accelerators, HW-algorithm co-design and low-power edge processing. Before that, she received a PhD from KU Leuven in 2008 and worked as a research scientist at Intel Labs, Hillsboro OR from 2008 till 2011. Marian is a topic chair of the DATE and ISSCC executive committees, TPC member of VLSI and ESSCIRC and was the chair of tinyML2021 and TPC co-chair of AICAS2020. Marian is an IEEE SSCS Distinguished Lecturer, was a member of the Young Academy of Belgium, an associate editor for TVLSI, TCAS-II and JSSC and a member of the STEM advisory committee to the Flemish Government. Marian received the André Mischke YAE Prize for Science and Policy in 2021, and was awarded the InspiringFifty Deep Tech BeneLux 2021 prize.
Friday October 21st
10:45 - 11:45
10:45 - 11:45
Mixed-Signal Design on next-generation SoCs for the Intelligently Connected World
Dr. Keith O'Donoghue, Director of Engineering, Qualcomm
Abstract: The challenge of Analog/Mixed-Signal IP Design on next-generation SoCs for the Connected World is multi-faceted. The continual push to drive power, performance and area metrics across a range of advanced technology nodes is a huge challenge for design, verification and physical implementation teams. This talk will discuss how high-performance IP teams need a strong focus on innovation, design methodology and advanced toolsets to ensure next-generation SoCs can meet the vast market opportunity being ushered in by the intelligently connected world.
Dr. Keith O'Donoghue is Director of Engineering of the Analog/Mixed-Signal IP design team at Qualcomm, Cork, Ireland since 2018. He received the B.Eng. and M.Eng.Sc. degrees in Microelectronic Engineering from University College Cork in 2004 and 2005 respectively and the Ph.D. degree in Electrical and Computer Engineering from the University of California at Davis in 2009 in the area of switched-capacitor sigma-delta ADCs. From 2009 to 2018 he worked as an Analog/RF IC Design Engineer on various low-power mixed-signal products for both Cypress Semiconductor and Analog Devices. He has 7 granted U.S. patents in the area of precision AFEs and Data Converter Systems and is currently Adjunct Senior Lecturer at University College Cork, Ireland where he teaches a graduate level course in Data Converter Systems Design.