Thursday October 20th
9:15 - 10:15
9:15 - 10:15
Enabling tinyML by exploiting heterogeneous multi-core AI processing
Prof. Marian Verhelst, KU Leuven
Abstract: tinyML strives for powerful machine inference in resource-scarce distributed devices. To allow intelligent applications at ultra-low energy and low latency, one needs 1.) compact compute and memory structures; 2.) which are used at very high utilization. This has resulted in a wide variety of accelerator designs proposed in the SotA. However, it becomes increasingly clear that every intelligent edge device will need to be equipped with a diverse set of many heterogeneous co-processors, which allow to run every workload at the most compatible (combination of) accelerators. Moreover, by using multiple cores in parallel, streaming data between the cores, the required amount of on-chip memory and IO bandwidth can be reduced, leading to area, energy and latency savings. This talk will introduce the benefits and challenges of such heterogeneous ML systems, supported through practical examples for efficient deep inference.
Marian Verhelst is a full professor at the MICAS laboratories of the EE Department of KU Leuven. Her research focuses on embedded machine learning, hardware accelerators, HW-algorithm co-design and low-power edge processing. Before that, she received a PhD from KU Leuven in 2008 and worked as a research scientist at Intel Labs, Hillsboro OR from 2008 till 2011. Marian is a topic chair of the DATE and ISSCC executive committees, TPC member of VLSI and ESSCIRC and was the chair of tinyML2021 and TPC co-chair of AICAS2020. Marian is an IEEE SSCS Distinguished Lecturer, was a member of the Young Academy of Belgium, an associate editor for TVLSI, TCAS-II and JSSC and a member of the STEM advisory committee to the Flemish Government. Marian received the André Mischke YAE Prize for Science and Policy in 2021, and was awarded the InspiringFifty Deep Tech BeneLux 2021 prize.
Friday October 21st
10:45 - 11:45
10:45 - 11:45
Mixed-Signal Design on next-generation SoCs for the Intelligently Connected World
Dr. Keith O'Donoghue, Director of Engineering, Qualcomm
Abstract: The challenge of Analog/Mixed-Signal IP Design on next-generation SoCs for the Connected World is multi-faceted. The continual push to drive power, performance and area metrics across a range of advanced technology nodes is a huge challenge for design, verification and physical implementation teams. This talk will discuss how high-performance IP teams need a strong focus on innovation, design methodology and advanced toolsets to ensure next-generation SoCs can meet the vast market opportunity being ushered in by the intelligently connected world.
Dr. Keith O'Donoghue is Director of Engineering of the Analog/Mixed-Signal IP design team at Qualcomm, Cork, Ireland since 2018. He received the B.Eng. and M.Eng.Sc. degrees in Microelectronic Engineering from University College Cork in 2004 and 2005 respectively and the Ph.D. degree in Electrical and Computer Engineering from the University of California at Davis in 2009 in the area of switched-capacitor sigma-delta ADCs. From 2009 to 2018 he worked as an Analog/RF IC Design Engineer on various low-power mixed-signal products for both Cypress Semiconductor and Analog Devices. He has 7 granted U.S. patents in the area of precision AFEs and Data Converter Systems and is currently Adjunct Senior Lecturer at University College Cork, Ireland where he teaches a graduate level course in Data Converter Systems Design.
Friday October 21st
15:45 - 16:45
15:45 - 16:45
The MOS Device - Cornerstone of Quantum Computing
Prof. Andrei Vladimirescu, Delft University of Technology, Univ. of California, Berkeley
Abstract: Advances in semiconductor and superconductor technology have sparked a new round of research in quantum computing in recent years. Quantum computers hold the promise to efficiently solve problems that are intractable by today’s electronic computers. In a quantum computer, standard logic bits ‘1’ and ‘0’ are replaced by quantum states |0ñ and |1ñ referred to as quantum bits (qubits). The challenge facing researchers is controlling and detecting these quantum states, which are preserved long enough only at deep sub-Kelvin temperatures.
Physical qubits in existing quantum processors are implemented as either the spin of an electron or the state of a superconducting resonator (Josephson Junction). Semiconductor materials are used for most implementations. This talk will make the case for the advantages of electron spin qubit implementations using semiconductor technology, when all layers of a quantum computer are considered.
In addition to the physical qubits representing the core of the quantum processor, performing operations on qubits requires an electronic interface for their control, which today is implemented with standard instrumentation placed at room temperature. This may work as proof of concept for the low number of qubits available today; however, as the race for increasing the number of qubits is on with 100 this year and 1000 in a couple of years, the number of qubits will grow to hundreds of thousands or maybe millions as needed for the solution of practical problems, making room-temperature electronics for control unworkable due to the wiring requirements, signal integrity and cost.
The solution is to build the control electronics to operate at 4 K or below close to the qubits; Standard CMOS is the obvious technology of choice allowing both cryogenic operation (4 K down to 100 mK) and the integration on a single chip of the billions of transistors required to operate a very large number of qubits.
The challenges and feasibility of building integrated circuits (IC) operating at 4 K and below will be described in this presentation. All aspects will be considered starting with the operation of semiconductor devices at cryogenic temperatures and the physics governing this behavior, the development of compact device models reproducing the physical behavior, the CMOS IC design methodology in conjunction with the qubit behavior, and the implementation and measurement of state-of-the-art sense and control ICs operating at 4 K. These circuits and systems must satisfy very stringent requirements for precise control of the qubit state and sensing tiny electrical signals with extreme accuracy while operating under a strict power budget below 1 mW/qubit imposed by the cooling limits of existing refrigeration technology.
Andrei Vladimirescu (LF’17) received the M.S. and Ph.D. degrees in EECS from the University of California, Berkeley, where he was a key contributor to the SPICE simulator, releasing the SPICE2G6 production-level SW in 1981. He pioneered electrical simulation on parallel computers with the CLASSIE simulator as part of his PhD. He is the author of "The SPICE Book" published by J. Wiley and Sons.
For many years Andrei was R&D director leading the design and implementation of innovative Electronic Design Automation (EDA) products in software and hardware for Analog Devices Inc., Daisy Systems, Analog Design Tools, Valid Logic and Cadence.
Currently he is Professor involved in research projects at the University of California at Berkeley and the Technical University of Delft as well as consultant to industry. His research activities are in the areas of low-voltage low-power CMOS, design, simulation and modeling, circuits with new devices and circuits for quantum computing.
Andrei is an IEEE Life Fellow and IEEE CASS Vice-president of Conferences.